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Lattice Semiconductor
Convolutional Encoder User’s Guide
8. Double click on the Constraint Editor . You can enter the required preferences, including pin locking, using the
constraint editor. You can also create an ASCII preference ?le using a text editor. For additional details on the
ispLEVER preference language, refer to the ispLEVER online documentation.
9. Double click on Map Design . This will map the design into the physical elements of the target device. If there
are no errors in this process, you will see a green mark next to the Map Design process (Figure 19).
10. Double click on Place & Route Design . This will place and route the mapped design. If there are no errors in
this process, a green mark appears next to the Place & Route Design process (Figure 19).
ispLEVER Software Flow for ispXPGA Devices
1. Create a project directory.
2. Copy the synthesized design EDIF ?le and the Viterbi Decoder core netlist to the project directory.
3. Launch the ispLEVER software. Figure 16 shows the ispLEVER Project Navigator Window.
4. Select File > New Project and create or browse to the project directory. All design ?les will be generated in this
directory. Figure 5 shows the New Project Creation Dialog Box . Type project name and select EDIF as a
project type.
5. Double click on the device name in the Process Window of the Project Navigator and select the device.
Figure 6 shows the Device Selection Dialog Box .
6. Select Source > Import . The Import File Dialog Box is shown in Figure 24. Enter the EDIF ?lename and click
Open . The Import EDIF Dialog Box is shown in Figure 18. Select the EDIF vendor type and click OK . The
EDIF ?le will be added to the project.
7. Double click on Build Database . This will read the EDIF netlist and generates the design database. If there are
no errors in the process, you will see a green mark next to the Build Database process (Figure 19).
8. Double click on the Constraint Editor . You can enter the required preferences including pin locking using the
Constraint Editor. You can also create an ASCII constraint ?le using a text editor. For additional details on the
ispXPGA constraints, refer to the ispLEVER online documentation.
9. Double click on the Pack & Place Design . This will pack and place the design into the physical elements. If
there are no errors in the process, you will see a green mark next to the Pack & Place Design process.
10. Double click on the Route Design . This will route the pack and placed design. If there are no errors in the pro-
cess, you will see a green mark next to the Route Design process.
11. Double click on the Timing Analysis . This will execute static timing analyzer on the routed design. If there are
no errors in the process, you will see a green mark next to the Timing Analysis process.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
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